/* GAL 2 (Main logic) for SYS-Check V2.2      08/2015 by tfhh            */

CHIP   MAIN   GAL22V10

A15   A14  A13   A12   A11   PB7   PHI2  PHI2S  RW   OSSEL  MEMSEL  GND
EMEM  EOS  OSCS  RCS   XRAM  RWE   ROE   FWE    REF  HIAD   PB0     VCC
 
/HIAD = PHI2S * /RW * A15 * A14 * /A13 * A12 * /A11;                     /* write access to $D0xx-$D7xx as combined signal for GAL 1 */

/ROE  = PHI2S * RW;                                                      /* OutputEnable for SRAM and Flash-ROM */

/RWE  = /RCS * /RW * PHI2S;                                              /* WriteEnable for SRAM */

/FWE = /OSCS * /RW * PHI2S;                                              /* WriteEnable for Flash-ROM */

/RCS  = /EMEM * /MEMSEL * /A15 * /A14                                    /* ChipEnable SRAM ($0000-$3FFF) */
      + /EMEM * /MEMSEL * /A15 *  A14 * /A13 * /A12                      /* ChipEnable SRAM ($4000-$4FFF) */
      + /EMEM * /MEMSEL * /A15 *  A14 * /A13 *  A12 * /A11 * PB7 * PB0   /* ChipEnable SRAM ($5000-$57FF) */
      + /EMEM * /MEMSEL * /A15 *  A14 * /A13 *  A12 * /A11 * /PB0        /* ChipEnable SRAM ($5000-$57FF) */
      + /EMEM * /MEMSEL * /A15 *  A14 * /A13 *  A12 *  A11               /* ChipEnable SRAM ($5800-$5FFF) */
      + /EMEM * /MEMSEL * /A15 *  A14 *  A13                             /* ChipEnable SRAM ($6000-$7FFF) */
      + /EMEM * /MEMSEL * A15 * /A14                                     /* ChipEnable SRAM ($8000-$BFFF) */
      + /EMEM * /MEMSEL * A15 *  A14 * /A13 * /A12 * /PB0                /* ChipEnable SRAM ($C000-$CFFF) */
      + /EMEM * /MEMSEL * A15 *  A14 * /A13 *  A12 * A11 * /PB0          /* ChipEnable SRAM ($D800-$DFFF) */
      + /EMEM * /MEMSEL * A15 *  A14 *  A13 * /PB0                       /* ChipEnable SRAM ($E000-$FFFF) */
      + /XRAM;                                                           /* ChipEnable SRAM ($4000-$7FFF) extended memory */

/OSCS = PB0 * /EOS * /OSSEL *  A15 * A14 *  A13                               /* ChipEnable Flash-ROM, range $E000-$FFFF */
      + PB0 * /EOS * /OSSEL *  A15 * A14 * /A13 *  A12 *  A11                 /* ChipEnable Flash-ROM, range $D800-$DFFF */
      + PB0 * /EOS * /OSSEL * /A15 * A14 * /A13 *  A12 * /A11 * /PB7 * XRAM   /* ChipEnable Flash-ROM, range $5000-$57FF */ 
      + PB0 * /EOS * /OSSEL *  A15 * A14 * /A13 * /A12;                       /* ChipEnable Flash-ROM, range $C000-$CFFF */

/REF = /OSCS + /RCS;                                                     /* REF=0 when accessing ROM or RAM on Sys-Check PCB */


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